The present invention relates to electrical devices, e.g., semiconductor integrated circuit devices, having in-laid (xe2x80x9cdamascenexe2x80x9d-type) metallization patterns, e.g., interconnection lines, etc., and to a method for minimizing, or substantially preventing, deleterious electromigration of the metallic element(s) of the metallization pattern. More specifically, the present invention relates to semiconductor devices comprising copper (Cu) interconnection patterns and is applicable to manufacture of high speed integrated circuits having sub-micron dimensioned design features and high electrical conductivity interconnect structures.
The present invention relates to a method for forming metal films as part of metallization processing of particular utility in the manufacture of electrical and electronic devices, e.g., circuit boards and semiconductor integrated circuits, and is especially adapted for use in processing employing xe2x80x9cin-laidxe2x80x9d or xe2x80x9cdamascenexe2x80x9d-type technology.
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized (e.g., 0.18 xcexcm and under), low resistance-capacitance (RC) time constant metallization patterns, particularly wherein the sub-micron-sized metallization features, such as vias, contact areas, lines, etc. require grooves, trenches, and other shaped openings or recesses having very high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon (Si) or, in some instances, gallium arsenide (GaAs), and a plurality of sequentially formed interlayer dielectrics and electrically conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter-wiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced-apart metallization layers or strata are electrically interconnected by a vertically oriented conductive plug filling a via hole formed in the inter-layer dielectric layer separating the layers or strata, while another conductive plug filling a contact area hole establishes electrical contact with an active device region, such as a source/drain region of a transistor, formed in or on the semiconductor substrate. Conductive lines formed in groove- or trench-like openings in overlying inter-layer dielectrics extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more layers or strata of such metallization in order to satisfy device geometry and microminiaturization requirements.
Electrically conductive films or layers of the type contemplated for use in e.g., xe2x80x9cback-endxe2x80x9d semiconductor manufacturing technology for fabricating devices having multi-level metallization patterns such as described supra, typically comprise a metal such as titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr), nickel (Ni), cobalt (Co), silver (Ag), gold (Au), copper (Cu) and their alloys. In use, each of the enumerated metals presents advantages as well as drawbacks. For example, Al is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid xe2x80x9cwetxe2x80x9d type technology such as electrodeposition, step coverage with Al is poor when the metallization features are scale down to sub-micron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electro-migration. In addition, certain low dielectric constant materials, e.g., polyimides, when employed as dielectric inter-layers, create moisture/bias reliability problems when in contact with Al.
Copper (Cu) and Cu-based alloys are particularly attractive for use in large scale integration (LSI), very large-scale integration (VLSI), and ultra-large scale (ULSI) semiconductor devices requiring multi-level metallization systems for xe2x80x9cback-endxe2x80x9d processing of the semiconductor wafers on which the devices are based. Cu- and Cu alloy-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing Al and its alloys, as well as a higher (but not complete) resistance to electromigration. Moreover, Cu and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably Ag and Au. Also, in contrast to Al and the refractory-type metals (e.g., Ti, Ta, and W), Cu and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
As indicated above, a commonly employed method for forming xe2x80x9cin-laidxe2x80x9d metallization patterns as are required for xe2x80x9cback-endxe2x80x9d metallization processing of semiconductor wafers employs xe2x80x9cdamascenexe2x80x9d-type technology. Generally, in such processing methodology, a recess (i.e., an opening) for forming, e.g., a via hole in a dielectric layer for electrically connecting vertically separated metallization layers, or a groove or trench for a metallization line, is created in the dielectric layer by conventional photolithographic and etching techniques, and filled with a selected metal. Any excess metal overfilling the recess and/or extending over the surface of the dielectric layer is then removed by, e.g., chemical-mechanical polishing (CMP), wherein a moving pad is biased against the surface to be polished/planarized, with the interposition of a slurry containing abrasive particles (and other ingredients) therebetween.
A variant of the above-described technique, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive via plug in electrical contact with a conductive line.
Referring now to FIG. 1, schematically shown therein in simplified cross-sectional view, is a conventional damascene-type processing sequence employing relatively low cost, high manufacturing throughput plating and CMP techniques for forming recessed xe2x80x9cback-endxe2x80x9d metallization patterns (illustratively of Cu-based metallurgy but not limited thereto) in a semiconductor device formed in or on a semiconductor wafer substrate 1. In a first step, the desired arrangement of conductors is defined as a pattern of recesses 2 such as via holes, grooves, trenches, etc. formed (as by conventional photolithographic and etching techniques) in the surface 4 of a dielectric layer 3 (e.g., a silicon oxide and/or nitride or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate 1. In a second step, a layer of Cu or Cu-based alloy 5 is deposited by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the recesses 2. In order to ensure complete filling of the recesses, the Cu-containing layer 5 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer of excess thickness t so as to overfill the recesses 2 and cover the upper surface 4 of the dielectric layer 3. Next, the entire excess thickness t of the metal overburden layer 5 over the surface of the dielectric layer 3 is removed by a CMP process utilizing an alumina (Al2O3)-based slurry, leaving metal portions 5xe2x80x2 in the recesses 2 with their exposed upper surfaces 6 substantially co-planar with the surface 4 of the dielectric layer 3.
The above-described conventional damascene-type process forms in-laid conductors 5xe2x80x2 in the dielectric layer 3 while avoiding problems associated with other types of metallization patterning processing, e.g., blanket metal layer deposition, followed by photolithographic masking/etching and dielectric gap filling. In addition, such single or dual damascene-type processing can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, and with a plurality of metallization levels, i.e., five or more levels.
A drawback associated with Cu-based xe2x80x9cback-endxe2x80x9d metallization is the possibility of Cu diffusion into adjacent structures, e.g., an underlying semiconductor substrate (typically Si) or a dielectric layer, resulting in degradation of semiconductive or insulative properties, as well as poor adhesion of the deposited Cu or Cu alloy layer to various materials employed as dielectric inter-layers, etc. As a consequence of these phenomena associated with Cu-based metallurgy, it is generally necessary to provide an adhesion promoting and/or diffusion barrier layer intermediate the semiconductor substrate and the overlying Cu-based metallization layer. Suitable materials for such adhesion/barrier layers include, e.g., Ti, W, Cr, Ta, and TaN.
Another drawback associated with the use of Cu or Cu-based metallurgy for xe2x80x9cback-endxe2x80x9d metallization processing of semiconductor devices, results from the undesirable formation of copper oxide(s), e.g., Cu2O, CuO, CuO2, etc., on the planarized Cu or Cu-based alloy surfaces of the in-laid metallization features as a result of oxidation, etc., due to the strong chemical oxidizing agents conventionally included in CMP slurries for enhancing Cu dissolution/removal rates or as a result of exposure of the freshly abraded Cu-based surfaces to an oxidizing atmosphere, e.g., air or oxygen. The thickness of the copper oxide layer can vary depending upon the particular CMP processing conditions, e.g., stronger oxidizing agents contained in the CMP slurry result in thicker oxide layers, as does increased duration of exposure of freshly abraded, post CMP Cu surfaces to oxidizing atmospheres, e.g., air.
Such copper oxide-containing layer(s) disadvantageously increase contact resistance and reduce or prevent adhesion of layers thereto, e.g., silicon nitride-based capping layers. Moreover, the copper oxide layers are brittle, increasing the likelihood of circuit disconnect or reduced conductivity due to separation, as by peeling, of the copper oxide layer from conductor layers in contact therewith. Yet another significant disadvantage attributable to the presence of copper oxide at the interface between adjacent electrical conductors results from the rapid diffusion of Cu atoms and/or ions along the oxide layer. The latter characteristic of copper oxide layers disadvantageously results in enhanced material transport during electrical current flow and thus increases the electromigration rate of Cu atoms and/or ions along Cu-based conductor lines.
Electromigration occurs in extended runs or lengths of metal conductor lines carrying significant currents. According to a conventional theory for explaining the mechanism of electromigration, the current flow within the conductor line can be sufficient to result in movement of metal (Cu) atoms and/or ions along the line via momentum transfer engendered by collision of the metal (Cu) atoms and/or ions with energetic, flowing electrons. The current flow also creates a thermal gradient along the conductor length which increases the mobility of the metal ions and/or atoms. As a consequence of the momentum transfer and the thermally enhanced mobility, metal (Cu) atoms and/or ions diffuse in the direction of the current flow, and metal loss at the source end of the conductor eventually results in thinning of the conductor line. The electromigration effect can continue until the conductor line becomes so thin that it separates from the current input or forms an open circuit, resulting in circuit (i.e., semiconductor chip) failure. As this usually occurs over an extended period of operation, the failure is often seen by the end-user.
As design rules for high integration density, high speed semiconductor devices extend deeper into the sub-micron range, e.g., about 0.18 xcexcm and under, e.g., about 0.15 xcexcm and below, and the number of metallization levels increases, the reliability of the xe2x80x9cback-endxe2x80x9d interconnection patterns and systems become particularly critical for the obtainment of desired operating characteristics and performance.
Thus, there exists a need for metallization process methodology which avoids the above-mentioned drawbacks associated with oxide layer formation, electromigration, etc., and which enables formation of metallization members, e.g., interconnect and routing lines, particularly of Cu or Cu-based alloys, having high reliability, high product yield, improved electromigration resistance, and high performance. In particular, there exists a need for eliminating the problems associated with electromigration and oxide layer formation resulting from CMP processing to form xe2x80x9cin-laidxe2x80x9d, xe2x80x9cdamascene-typexe2x80x9d Cu-based metallization patterns. Moreover, there exists a need for improved metallization processing technology which is fully compatible with conventional process flow, methodology, and throughput requirements in the manufacture of integrated circuit semiconductor devices and other devices requiring xe2x80x9cin-laidxe2x80x9d metallization patterns.
An advantage of the present invention is a method of manufacturing an electrical or electronic device having highly reliable, electromigration-resistant metallization patterns.
Another advantage of the present invention is a method of manufacturing a semiconductor integrated circuit device having highly reliable, electromigration-resistant Cu-based metallization patterns.
Yet another advantage of the present invention is a method of manufacturing xe2x80x9cin-laidxe2x80x9d, xe2x80x9cdamascenexe2x80x9d-type Cu-based metallization patterns having improved reliability, high conductivity, and improved electromigration resistance.
Still another advantage of the present invention is an improved method of forming high-density, xe2x80x9cin-laidxe2x80x9d metallization patterns by a xe2x80x9cdamascenexe2x80x9d-type, CMP-based process which is fully compatible with existing process methodology for forming integrated circuit semiconductor devices and printed circuit boards.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or will be learned from the practice of the invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing an electrical device, the method comprising the sequential steps of:
(a) providing a substrate including at least one damascene-type, metal feature in-laid in the upper, exposed surface of a layer of dielectric material overlying at least a portion of the substrate, the at least one metal feature including an upper, exposed surface substantially co-planar with the upper surface of the layer of dielectric material;
(b) selectively depositing on the exposed upper surface of the at least one metal feature at least one layer comprising at least one metallic passivant element for passivating the upper surface of the at least one metal feature; and
(c) effecting reaction between at least a portion of the at least one layer comprising at least one metallic passivant element and the upper surface of the at least one metal feature to form a passivating layer there at, whereby electromigration of the metal of the at least one metal feature is minimized or substantially prevented.
According to embodiments of the present invention, the method further comprises the step of:
(d) selectively removing any remaining reacted and/or unreacted portion(s) of the at least one layer comprising at least one metallic passivant element which extend(s) above the upper surface of the layer of dielectric material, thereby making the upper surface of the at least one in-laid metal feature substantially co-planar with the upper surface of the layer of dielectric material.
In accordance with embodiments of the present invention, the electrical device comprises a semiconductor integrated circuit device, and step (a) comprises providing as the substrate a semiconductor wafer of monocrystalline silicon (Si) or gallium arsenide (GaAs) having a major surface, the dielectric layer is formed over at least a portion of the major surface, the at least one damascene-type, in-laid metal feature comprises a plurality of features of different widths and/or depths for providing vias, inter-level metallization, and/or interconnection lines of at least one active device region or component formed on or within the semiconductor wafer, and the metal of the at least one in-laid metal feature is unalloyed copper (Cu); and step (b) comprises selectively depositing, as by electroless deposition or chemical vapor deposition (CVD), at least one layer comprising at least one metallic passivant element capable of chemically reducing any copper oxide present on the upper surface of the at least one Cu metal feature, the at least one metallic passivant element being selected from the group consisting of: magnesium (Mg), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), palladium (Pd) and chromium (Cr).
In embodiments according to the present invention, step (c) is performed substantially simultaneously with step (b), e.g., at ambient temperatures; whereas according to other embodiments of the present invention, step (c) is performed after step (b), as by annealing in an inert atmosphere; and step (d) comprises selectively removing, as by etching or chemical-mechanical polishing (CMP), any remaining elevated, reacted and/or unreacted portion(s) of the layer comprising at least one metallic passivant element which extend(s) above the upper surface of the layer of dielectric material, thereby making the upper surface of the at least one in-laid metal feature substantially co-planar with the upper surface of the dielectric layer.
According to further embodiments of the present invention, step (a) for providing the substrate including at least one damascene-type, in-laid metal feature comprises the preliminary steps of:
i. forming a dielectric layer on a surface of a substrate, the dielectric layer having an exposed, upper surface;
ii. forming at least one recess in the exposed, upper surface of the dielectric layer;
iii. depositing a metal layer filling the at least one recess and extending over the upper surface of the dielectric layer;
iv. removing the portion(s) of the metal layer extending over the upper surface of the dielectric layer; and
v. removing (e.g., by CMP) any excess thickness portion(s) of the metal layer filling the at least one recess which extend(s) above the upper surface of the dielectric layer, thereby making the upper, exposed, upper surface of the at least one in-laid metal feature substantially co-planar with the exposed, upper surface of the dielectric layer.
According to another aspect of the present invention, a method of manufacturing a semiconductor integrated circuit device comprises the sequential steps of:
(a) providing a substrate comprising a semiconductor wafer of monocrystalline Si or GaAs and having a major surface, a dielectric layer formed on at least a portion of the major surface and having an exposed, upper surface, at least one damascene-type, unalloyed Cu metal feature in-laid in the exposed, upper surface of the dielectric layer, the at least one Cu metal feature including an exposed, upper surface substantially co-planar with the exposed, upper surface of the dielectric layer;
(b) selectively depositing at least one layer comprising at least one metallic passivant element for the Cu metal feature on the upper surface of the at least one Cu metal feature, the at least one metallic passivant element being capable of chemically reducing any copper oxide present on the upper surface of the at least one metal feature and selected from the group consisting of: magnesium (Mg), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), palladium (Pd), and chromium (Cr); and
(c) effecting reaction between at least a portion of the at least one layer comprising at least one metallic passivant element and the upper surface of the at least one Cu metal feature to form a passivating layer there at, whereby electromigration of Cu atoms and/or ions from the at least one Cu metal feature is minimized or substantially prevented.
According to embodiments of the present invention:
step (a) comprises providing a semiconductor wafer having a dielectric layer on a major surface thereof which comprises a plurality of in-laid, unalloyed Cu metal features of different widths and/or depths for providing vias, inter-level metallization, and/or interconnection lines of at least one active device region or component formed on or within the semiconductor wafer;
step (b) comprises selectively depositing the at least one layer comprising at least one metallic passivant element by electroless deposition or chemical vapor deposition (CVD); and
step (c) is performed substantially simultaneously with step (b) at ambient temperature or subsequent to step (b) by annealing at an elevated temperature in an inert atmosphere.
According to still further embodiments of the present invention, the method comprises the further step of:
(d) selectively removing any elevated, remaining reacted and/or unreacted portion(s) of the at least one layer comprising at least one metallic passivating element which extend(s) above the upper surface of the layer of dielectric material, thereby making the upper surface of the at least one in-laid, Cu metal feature substantially co-planar with the upper surface of the dielectric layer.
Additional advantages of the present invention will readily become apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be understood, the present invention is capable of other and different embodiments, and its several details are capable of modification in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.